The present invention relates generally to semiconductor memory, and more particularly to a high-speed dynamic random access memory (DRAM)-based memory cell having transparent refresh.
In a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), data is stored as a logic HIGH (e.g., xe2x80x9c1xe2x80x9d) or logic LOW (e.g., xe2x80x9c0xe2x80x9d) by the presence or absence of charge on a capacitor within an individual memory cell. After the data has been stored as charge on the capacitor, the charge gradually leaks off and the data is corrupted. Therefore, a xe2x80x9crefreshxe2x80x9d cycle must be performed to maintain the integrity of the data.
To refresh data in a memory array, the array is typically placed in a read mode to obtain the present data stored in a row of memory cells. Subsequently, this data is used as new input data that is re-written into the row of memory cells, thus maintaining the stored data.
A static random access memory (SRAM), as contrasted with a DRAM, holds its data for as long as power is supplied to the circuit without the need for a refresh cycle. The lack of necessity to refresh memory cell contents is one of the reasons why DRAM memory speeds lag that of SRAM. Along with the benefits of SRAM, however, comes a high manufacturing cost as compared with DRAM. A typical SRAM cell consists of 6 transistors as compared with one transistor for a DRAM cell. Notwithstanding the higher manufacturing costs and space requirements associated with SRAM cells, there are certain applications that can and do take advantage of the higher speeds associated with SRAMs. Accordingly, it would be advantageous to have the high-speed associated with SRAMs along with the lower manufacturing costs associated with DRAMs combined into a memory cell architecture having a hidden refresh.
The present invention provides a high-speed transparent refresh DRAM-based memory cell and architecture. According to an exemplary embodiment of the invention, each memory cell consists of 4 transistors configured to incorporate differential data storage (i.e., storing a true logic state and a complementary logic state), with each pair of transistors having a dual port configuration and forming one of a complementary pair of storage nodes for the memory cell. Each memory cell is coupled to 2 wordlines and 4 digit lines. Since the memory cell stores complementary data, and since a logic LOW state is rewritten to a given memory cell faster than a logic HIGH state is rewritten, the logic LOW state is rewritten and the complementary logic state is known to be a logic HIGH state. As a result, by using complementary data states within each stored bit, both the logic LOW and logic HIGH states are rewritten to the memory cell faster than independently writing a logic HIGH state.